ET4US

Epitaxial Technologies for Ultimate  Scaling

homeproject summaryconsortium membersresults highlights,  events, restricted access contact us  
 


PROJECT SUMMARY

OBJECTIVES
     

Silicon CMOS is rapidly running out of steam and its last incarnation could well be in the form of the strained silicon (SS) transistor. The entire semiconductor industry is puzzled about what comes next as the roadmap advances towards the terahertz region. It is also clear that virtually every material (gate, gate oxide and channel) that is used in the current transistor must be replaced within by the end of the decade. All of that must take place without any interruption in the pace of the industry, a crucial requirement.
 

Two main high mobility material classes are emerging as potential silicon replacement, namely germanium (Ge) and compound semiconductors (CS). The goal of this project is to find out which one presents the best future technology platform. This requires a major rethinking of all materials and processes and it will be addressed here from all technologically relevant aspects: advanced large area wafers, novel gate stacks and transistor processing. With a strict focus on a simple and well defined process-flow as well as an innovative, fast materials characterization track, the main strengths and show-stoppers for each materials system will be identified.  
 

The first technological objective is to demonstrate that device quality large area compliant substrates of Ge- on-insulator (GOI) and CS-on-insulator (CSOI) can be obtained. GOI and CSOI will be grown by developing a “strained oxide template on Si” technology based on molecular beam epitaxy (MBE).
 

The second technological objective is to demonstrate high quality gate stacks on Ge and CS. The challenge is to find a suitable set of high k compound materials that can be used as gate dielectrics while maintaining high channel mobilities. The development of amorphous or epitaxial (for double gate) metal gates is an essential component of this research program.  
 

The third technological objective is to integrate the new channel and gate materials with a 200 mm semiconductor wafer processing line to demonstrate high mobility transistors for a few well chosen material systems
 

WORKPLAN