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1) Objective I (Technological): Demonstrate the co-integration of functional high-μ Ge pMOS and III-V nMOS on the same engineered substrate using 65 nm/200 mm platform. 2) Objective II (Scientific): Investigate short channel, leakage and transport effects and fundamental materials problems in aggressively scaled high channel mobility devices. 3) Objective III (Strategic): Prepare the take up of project results by end of year 2009 in a broader 22 nm or sub-22 nm technology platform which could be implemented in a future IP in FP7 ICT . |
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