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Organization / Principle Investigator |
Country |
RTD role |
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Project leader: |
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1 |
 |
National Center of Scientific Research - Demokritos
Dr. A. Dimoulas |
Greece |
-
Development of passivation methodologies and gate
dielectrics on Ge & III-V small area (two inch)
substrates
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Characterization (in-situ XPS and Kelvin probe, XRD and
electrical evaluation by MIS)
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Gate metals/workfunction
engineering
|
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Contractors: |
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2 |
 |
Interuniversity Microelectronics Center
Dr. M. Caymax |
Belgium |
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Dual-channel
engineered substrates / selective epitaxy
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Front-end processing
of III-V semiconductors in 65 nm/ 200 mm pilot line
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Dual channel Ge/III-V
transistors on engineered substrates
|
|
3 |
 |
IBM Research
GmbH / Zurich Research Laboratory
Dr. C. Marchiori |
Switzerland
|
-
Gate dielectric development with an emphasis on large
area (8 inch) III-V substrates.
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Development of growth of III-V active channels on
epi-GaAs/GeOI substrates
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Surface cleaning and passivation of III-V semiconductors
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4 |
 |
Commissariat l'
Energie Atomique
-LETI
Dr. C. Reita |
France |
-
Development of local GeOI/SOI by Ge condensation on 8
inch substrates
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Electrical evaluation of the substrates using
Ψ-MOSFETs
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TEM characterization of threading dislocations
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Raman characterization of strain
|
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5 |
 |
ST
Microelectronics-Crolles
Dr. D. Bensahel |
France |
-
On-wafer testing of short channel Ge pMOS and III-V nMOS
transistors on 200 mm substrates, with an emphasis on
channel mobility.
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Performance estimation using MASTAR software
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Benchmarking
with “best Si” tech.
|
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7 |
 |
AIXTRON
Prof. M. Heuken |
Germany |
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8 |
 |
UoG
University of Glasgow
Prof. A. Asenov |
U.K. |
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Monte Carlo modeling of III-V MOSFETs with an emphasis
to implant-free devices
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Simulation of Ge based transistors using TCAD tools
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Development of Au-free S/D contacts for III-V nMOSFETs
|
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9 |
 |
KULeuven
Katholike Universitaet Leuven
Prof. J.-P. Locquet |
Belgium |
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