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Seventh Framework Program : Information & Communication Technologies

FP7 ICT objective 3.1     

"Next Generation Nanoelectronics Components & Electronics Integration"


Dual-channel CMOS for (sub)-22 nm high performance logic

Specific Targeted Research Project
Starting date: 1/ 12/ 2007 ,  Duration: 42 months
Total budget: 9.131.402,07 Euro
  EC contribution: 5.799.338,52 Euro

DUALLOGIC, a top ranked project, is the "flagship of CMOS in FP7. The aim is to develop a high mobility  dual-channel Front-End of Line technology as an option for (sub)-22 nm high performance logic ICs. Unlike the present day devices which are all made of Si, we propose that the active channel of pMOS and nMOS transistors in future nanoelectronics could be made of different high mobility semiconductor materials.  In particular, we propose that pMOS are made of Ge and nMOS are made of III-V compound semiconductors co-integrated in the same complex engineered substrate as shown in the Figure below.

Contact:   Dr. A. Dimoulas,

Project Leader    

                      web master: Dr. Georgia Mavrou